環宇翔
博士，研究員(yuán)，研究組組長
Email: yxhuan@@gdiist.cn
個人簡介：
環宇翔，研究員(yuán)，類腦計算架構與超大(dà)規模處理系統研究組組長。2018年于複旦大(dà)學取得微電(diàn)子學與固體(tǐ)電(diàn)子學博士學位，曾任複旦大(dà)學信息科學與工(gōng)程學院任助理研究員(yuán)、江門市新會區威信高技術科學研究所副研究員(yuán)。長期圍繞領域專用處理架構（Domain-Specific Architecture, DSA）的芯片系統設計和領域應用開(kāi)展研究，重點聚焦于從芯片到系統的分(fēn)布式互聯處理架構和設計方法的研究，包括可重構可擴展架構的領域專用處理器、複雜(zá)深度學習模型的高能效加速和分(fēn)布式處理、神經拟态專用集成電(diàn)路和類腦計算系統等，累計發表學術論文30餘篇，申請發明專利15項。
類腦計算架構與超大(dà)規模處理系統課題組：
本課題組主要面向類腦計算的硬件處理架構和超大(dà)規模類腦計算系統設計展開(kāi)研究，旨在借鑒人腦的信息處理機制，設計具有神經拟态特性的專用處理内核、大(dà)規模的芯片互聯架構與方法、以及面向全腦尺度千億神經元規模超級計算系統。課題組将主要聚焦：面向類腦計算的領域專用處理架構與芯片設計，超低延時和高可靠的片上網絡互聯，面向晶圓級集成芯片的新型片上分(fēn)布式處理架構和任務調度方法。目标通過“算法-架構-電(diàn)路”協同設計的方法，實現事件驅動的超大(dà)規模芯片計算網絡，支持海量處理内核的局部數據共享、異步信息傳遞和分(fēn)布式協同處理，最終支撐千億神經元規模的類腦計算系統的設計構建。
代表論著：
[1] C. Ding#, Y. Huan#*, H. Jia, Y. Yan, F. Yang, L. Liu, M. Shen, Z. Zou and L.R. Zheng, "A Hybrid-Mode On-Chip Router for the Large-Scale FPGA-Based Neuromorphic Platform," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 69, no. 5, pp. 1990-2001, 2022. (SCI, 共同一(yī)作，共同通信作者)
[2] B. Huang#, Y. Huan#*, H. Jia, C. Ding, Y. Yan, B. Huang, L.R. Zheng, and Z. Zou, "AIOC: An All-In-One-Card Hardware Design for Financial Market Trading System," in IEEE Transactions on Circuits and Systems II: Express Briefs, 2022. (SCI, 共同一(yī)作，共同通信作者)
[3] Y. Jin, B. Huang, Y. Yan; Y. Huan*, J. Xu, S. Li, P. Gope, L. Xu, Z. Zou, and L.R. Zheng, "Edge-based Collaborative Training System for Artificial Intelligence-of-Things," in IEEE Transactions on Industrial Informatics, 2022. (SCI，共同通信作者)
[4] B. Huang#, Y. Huan#*, H. Chu, J. Xu, L.R. Zheng, and Z. Zou, “IECA: An In-Execution Configuration CNN Accelerator With 30.55 GOPS/mm² Area Efficiency,” in IEEE Transactions on Circuits and Systems I: Regular Papers, 2021. (SCI, 共同一(yī)作，通信作者)
[5] J. Xu#, Y. Huan#, B. Huang, H. Chu, Y. Jin, L.R. Zheng, Z. Zou, “A Memory-Efficient CNN Accelerator Using Segmented Logarithmic Quantization and Multi-Cluster Architecture,” in IEEE Transactions on Circuits and Systems II: Express Briefs, 2020. (SCI, 共同一(yī)作)
[6] Y. Huan, N. Ma, J. Mao, S. Blixt, Z. Lu, Z. Zou and L. R. Zheng, “A 101.4 GOPS/W Reconfigurable and Scalable Control-Centric Embedded Processor for Domain-Specific Applications,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 63, no. 12, pp. 2245-2256, Dec. 2016. (SCI)
[7] Y. Jin, J. Cai, J. Xu, Y. Huan*, Y. Yan, B. Huang, Y. Guo, L.R. Zheng, Z. Zou, “Self-aware distributed deep learning framework for heterogeneous IoT edge devices,” Future Generation Computer Systems, Volume 125, 2021. (SCI, 通信作者)
[8] W. Li, H. Chu, B. Huang, Y. Huan*, L.R. Zheng, Z. Zou, “Enabling on-device classification of ECG with compressed learning for health IoT,” Microelectronics Journal, Volume 115, 2021. (SCI, 通信作者)
[9] J. Xu#, Y. Huan#, B. Huang, H. Chu, Y. Jin, L.R. Zheng, Z. Zou, “Base-Reconfigurable Segmented Logarithmic Quantization and Hardware Design for Deep Neural Networks,” in Journal of Signal Processing Systems, 2020. (SCI, 共同一(yī)作)
[10] Y. Huan, J. Xu, L. Zheng, H. Tenhunen and Z. Zou, “A 3D Tiled Low Power Accelerator for Convolutional Neural Network,” 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, 2018. (EI)
